Intel Corp (INTC)

[ChipGeek]

Here's the more "complete" description (I use that term loosely ;p):

"When request for data from Core 1 results in a L1 cache miss, the request is sent to the L2 cache. If this request hits a modified line in the L1 data cache of Core 2, certain internal conditions may cause incorrect data to be returned to the Core 1."

If this problem made it through pre-silicon validation, plus 2 full steppings and a dash-stepping before being found and/or fixed, I would bet that the "certain internal conditions" is some esoteric combination of 7 obscure things that need to happen simultaneously.

Furthermore, I would guess that the effect of this would be similar to when one encounters bad DRAM...a system lockup or other noticeable problem. I don't think you'd just quietly get a wrong result and go on your merry way.

This is just a guess on my part, I have no visibility into this issue.

Perhaps an email into Intel support from their website asking for more specific information on this issue might yield some results.