Cadence Design Systems Inc (CDNS)

[ScovilleUnits]

:o)

Did you Win a Million $ last weekend at … http://www.sandiacasino.com/pages/info.html?

If not a Million-$, I’m thinking You you must have had a good time getting a sun tan and swimming and relaxing around their cool swimming pool? Lots of good food as well I’m sure and hey, how about Golf? Did you play some Golf too?

I have some pork chops and veggies on the grill calling my name….gotta go.

Have a great weekend my Friend!!!

[eastunder]

CDNS: Short Interest UP 21.6% to 16.4M in Mid Jul 2008

Friday , July 25, 2008 06:00ET

According to new short interest data from NASDAQ, short interest for Cadence Designs Systems, Incorporated (NasdaqNM: CDNS) INCREASED 21.6% to 16,394,094 shares as reported in mid-July, 2008.

SYMBOL CDNS
END JUNE 13,477,024
MID JULY 16,394,094
CHANGE +2,917,070
%CHANGE +21.64%
DAYS/COVER 5

Based on CDNS's 20-day average daily share volume of 3,351,610, it would require approximately 5 day(s) of buying to cover this short interest.

[eastunder]

okay...so maybe I should have added! :)

[ScovilleUnits]

15-Day (3-Week) Chart




~ ~ Safe to take a position here?... ‹(•¿•)›

[eastunder]

lol. Adjusted close aka Split adjustments? And I thought we could just click on an already adjusted line in a chart and grab those numbers. What happened to the good old days when we could use bigcharts interactive charts and get highs. lows and closes on each days line. I Don't think they span back 13 years, though!

I think I'll just do an educated guess! Or go ahead and just dump it at a HUGE loss. Debating that.

Wanna blow your mind? Look at the RMBS earnings. Can you believe that? Whoda thunk they would be that BAD? Not only will that gap fill tomorrow but a lower opp. is in the making?

UGH! Summer time!

[ScovilleUnits]

Please don’t tell me…

I have to wrap my head around summer 2008’s pps T/A activity as being related to the pps activity from 1st qtr 1995? Please say it ain’t so!

I want to go home now. I don’t like this game anymore…:o)

I’m actually trying to dodge your question cause the batteries in my calculator happenstanceually just now died a couple of seconds ago…Dang My Luck!…and so now I can’t mathamutize the “adjusted close” figgers.

Jan/Feb 1995 Historical Prices...
http://finance.yahoo.com/q/hp?s=CDNS&a=00&b=01&c=1995&d=01&e=28&f=1995&g=d

[eastunder]

Good job! At least we now know it's there.

It appears to have been a breakaway gap as indicated by volume, follow thru days, and new highs. Breakaways can take years to fill if they fill at all. We will see soon enough if it's one of those that just took years?

Can you get the gap number? The high of the 9th and the low of the 10th for me?

Also - There looks like one on the 7th of Feb 95 as well...although harder to see on this chart...can you pull that number also?

That will be first up if she heads that way.

Darn! Hate this part of the game. Don't even feel like owning it after their earnings report and forcast...but no need to take a beating when I have other cash and stocks in that portfolio. Guess I'm going longterm! or should I say...guess the 'eastunder' chicks are going longterm. :)

Bummer!

[ScovilleUnits]

Jan 10th perhaps?

[eastunder]

Jan 95? Better take a peak at that section.

[ScovilleUnits]

1-Yr chart...13 Years ago.

See any gaps ya like...:o)

[ScovilleUnits]

Those AMC reportings don’t leave a lot of timely room to maneuver around. Does it seem to you that after hour activity, following an AMC earnings announcement, can often reflect over reaction? Well, guess it wasn’t in this case?

Did you notice the volume? Could end the day around 4X the EMA(50) average.

[eastunder]

Can you believe it?
There's probably some old gap back there? :)

You probably didn't read their earnings but...LAWD! That was bad, Scov! I think it has gotten me twice in afterhours!

[ScovilleUnits]

Ouch!! "a 13-year low"




~ ~ Safe to take a position here?... ‹(•¿•)›

[eastunder]

Pretty impressive gap down. I wonder if it doesn't have a few more days of drama ahead of it?

[toytundra]

looking for a bounce in @6.99

[eastunder]

Cadence Design shares plunge to 13-year low; downgraded to sector perform at RBC

Thursday , July 24, 2008 10:12ET

BOSTON, Jul 24, 2008 (Thomson Financial via COMTEX) -- Shares of Cadence Design Systems Inc. tumbled to a 13-year low Thursday after the San Jose, Calif.-based company was downgraded to sector perform from outperform at RBC Capital, which cited the electronic design software maker's lowered 2008 revenue guidance.

The stock was down more than 30% to $7.12 on volume of 1.5 million shares, and hit a 13-year low of $6.99 earlier in the session. The issue's 30-day average volume is about 4.7 million shares.

Cadence cut its full-year revenue guidance to a range of $1.12 billion to $1.14 billion from a previous range of $1.49 billion to $1.54 billion. The current mean estimate of analysts polled by Thomson Reuters is for revenue of $1.51 billion.

"It would seem as though Moore's law is dead ... as management explained away a severe reduction in 2008 guidance by stating 'customers are staying on older process nodes longer'," RBC Capital analyst Mahesh Sanganeria said in a note to clients.

Sanganeria said customers "may indeed be deferring node-upgrade decisions" because of risk/reward reasons, but a more "mundane" explanation would be that Candence is seeing share loss.

"[W]e have lost visibility to a turn-around in revenue," Sanganeria said.

RBC Capital slashed its price target to $8 from $17.

The firm lowered its 2008 revenue estimate to $1.13 billion from $1.51 billion. Casey Logan cl/vj

[eastunder]

Cadence Design Systems Warns

(They certainly deserve to get smack down with this warning!)

Wednesday, July 23, 2008 18:21ET

Jul 23, 2008 (EarningsWhispers Guidance Summaries via Comtex) -- Cadence Design Systems Inc. (NASDAQ: CDNS) said it expects a third quarter loss of $0.11 to $0.09 per share on revenue of $235.0 million to $245.0 million.

The current consensus earnings estimate is $0.33 per share on revenue of $412.8 million for the quarter ending September 30, 2008.

****The company also said it expects 2008 earnings of $0.01 to $0.05 per share on revenue of $1.12 billion to $1.14 billion.***

(That's ridiculous!)

The company's previous guidance was earnings of $1.14 to $1.22 per share and continues to expect revenue of $1.49 billion to $1.54 billion and the current consensus earnings estimate is $0.90 per share on revenue of $1.51 billion for the year ending December 31, 2008.

This earnings guidance summary was provided by EarningsWhispers, a leading provider of earnings expectations - including corporate guidance announcements and analysts' expectations that differ from published estimates. http://www.earningswhispers.com

[eastunder]

CDNS: Q2 Adj EPS 14c vs 30c Meets 14c Est; Guidance Below Consensus

Wednesday, July 23, 2008 16:29ET

QUARTER RESULTS
Cadence Designs Systems, Incorporated (CDNS) reported Q2 results ended June 2008. Q2 Revenues were $329.48M; -15.73% vs yr-ago; BEATING revenue consensus by +4.60%. Q2 EPS was 2c. Adjusted Q2 EPS was 14c; -53.33% vs yr-ago; MATCHING earnings consensus.

Q2 RESULTS
Reported Revenues: $329.48M
Year-Ago $390.96M
Y/Y Chg -15.73%
Estimate $314.99M
SURPRISE +4.60%

EPS: 2c
Adj EPS: 14c
Year-Ago 30c
Y/Y Chg -53.33%
Estimate 14c
surprise 0.00%

GUIDANCE

Q3-08 Revenue Outlook [$235 - $245M]: The company expects total revenue in the range of $235 million to $245 million. The Q3-08 revenue forecast is below current consensus estimates.
Q3-08 Earnings Outlook [(11c) - (9c)]: Net loss per share using the non-GAAP measure is expected to be in the range of $(0.11) to $(0.09). The Q3-08 earnings forecast is below current consensus estimates.

FY-08 Revenue Outlook [$1120 - $1140M]: The company expects total revenue in the range of $1.120 billion to $1.140 billion. The FY-08 revenue forecast is below current consensus estimates.
FY-08 Earnings Outlook [1c - 5c]: Using the non-GAAP measure, diluted earnings per share for fiscal 2008 are expected to be in the range of $0.01 to $0.05. The FY-08 earnings forecast is below current consensus estimates.




ADDITIONAL COMMENTARY:
The Company's CEO stated that customers are demanding more flexibility in when, what and how they purchase software and hardware and as a result the Company lowered its outlook and transition to an approximately ninety-percent ratable license mix. The Company is projecting cash flow from operations of $175 million in 2008, and $250 million in 2009.



ORIGINAL EARNINGS RELEASE
Consensus estimate data provided by Reuters.
Visit Knobias.com for more indepth earnings information.

[eastunder]

CDNS...will gap down in the morning. 7.50 is current after hours. What a beating for those earnings even though they warned.

[eastunder]

Cadence Reports Q2 Revenue of $329 Million

Wednesday, July 23, 2008 16:05ET



SAN JOSE, CA -- (MARKET WIRE) -- 07/23/08 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today reported second quarter 2008 revenue of $329 million, compared to revenue of $391 million reported for the same period in 2007. On a GAAP basis, Cadence recognized net income of $5 million, or $0.02 per share on a diluted basis, in the second quarter of 2008, compared to net income of $60 million, or $0.20 per share on a diluted basis, in the same period in 2007.

In addition to using GAAP results in evaluating Cadence's business, management believes it is useful to measure results using a non-GAAP measure of net income, which excludes, as applicable, amortization of intangible assets, stock-based compensation expense, in-process research and development charges, certain termination and legal costs, integration and acquisition-related costs, gains or losses and expenses or credits related to non-qualified deferred compensation plan assets, executive severance payments, restructuring charges and credits, losses on extinguishment of debt and equity in losses (income) from investments. Non-GAAP net income is adjusted by the amount of additional taxes or tax benefit that the company would accrue if it used non-GAAP results instead of GAAP results to calculate the company's tax liability. See "GAAP to non-GAAP Reconciliation" below for further information on the non-GAAP measure.

Using this non-GAAP measure, net income in the second quarter of 2008 was $38 million, or $0.14 per share on a diluted basis, as compared to $91 million, or $0.30 per share on a diluted basis, in the same period in 2007.

"Although we achieved our Q2 numbers, it was more difficult than we planned. Customers are demanding still more flexibility in when, what and how they purchase software and hardware," said Mike Fister, chief executive officer. "As a result we've made the decision to lower our outlook and transition to an approximately ninety-percent ratable license mix. We believe this transition will enable us to keep our focus on the value of our technology. This decision is the right one for our business over the long term and for building and sustaining strong customer relationships into the future."

Kevin Palatnik, chief financial officer added, "A key metric for us, particularly as we move through this transition, is cash flow from operations. We are projecting cash flow from operations of $175 million in 2008, and $250 million in 2009."

The following statements are based on current expectations. These statements are forward looking, and actual results may differ materially. These statements do not include the impact of any mergers, acquisitions or other business combinations completed after June 28, 2008.

Business Outlook

For the third quarter of 2008, the company expects total revenue in the range of $235 million to $245 million. Third quarter GAAP net loss per share is expected to be in the range of $(0.27) to $(0.25). Net loss per share using the non-GAAP measure defined below is expected to be in the range of $(0.11) to $(0.09).

For the full year 2008, the company expects total revenue in the range of $1.120 billion to $1.140 billion. On a GAAP basis, net loss per share for fiscal 2008 is expected to be in the range of $(0.54) to $(0.50). Using the non-GAAP measure defined below, diluted earnings per share for fiscal 2008 are expected to be in the range of $0.01 to $0.05.

A schedule showing a reconciliation of the business outlook from GAAP net income and diluted net income per share to the non-GAAP net income and diluted net income per share is included with this release.

Audio Webcast Scheduled

Mike Fister, Cadence's president and chief executive officer, and Kevin Palatnik, Cadence's senior vice president and chief financial officer, will host a second quarter 2008 financial results audio webcast today, July 23, 2008, at 2 p.m. (Pacific) / 5 p.m. (Eastern). Attendees are asked to register at the Web site at least 10 minutes prior to the scheduled webcast. An archive of the webcast will be available starting July 23, 2008 at 5 p.m. (Pacific) and ending July 30, 2008 at 5 p.m. (Pacific). Webcast access is available at www.cadence.com/company/investor_relations.

[eastunder]

CDNS: To Release Q2 Results Jul 23 [AMC]

Wednesday, July 23, 2008 08:30ET

Cadence Designs Systems, Incorporated (Nasdaq NM: CDNS) is scheduled to release its Q2 financial results on July 23, 2008, after the close of the market (AMC).

CONSENSUS ESTIMATES:

Q2 Revenue: $314.99 million
Q2 EPS: $0.14 per share

PREVIOUS PERIOD:

Prev Q2 Revenue: $390.96 million
Prev Q2 EPS: $0.30 per share

ADDITIONAL INFORMATION

Original Confirmation

The Company will also hold a related conference call to discuss these results.

[ScovilleUnits]

An Assistant Test

~ ~



~ ~ Safe to take a position here?... ‹(•¿•)›

[eastunder]

Cadence Announces Second Quarter 2008 Financial Results Webcast

Thursday , July 03, 2008 16:05ET



SAN JOSE, CA -- (MARKET WIRE) -- 07/03/08 --


WHO:

Cadence Design Systems, Inc. (NASDAQ: CDNS) to announce second quarter 2008 financial results via Webcast.

WHAT:

You are invited to attend the second quarter 2008 financial results audio Webcast. Participating on the Webcast will be Mike Fister, president and chief executive officer, and Kevin Palatnik, senior vice president and chief financial officer.

WHEN:

The Webcast will begin Wednesday, July 23, 2008 at 2 p.m. (Pacific)/5 p.m. (Eastern). An archive of the Webcast will be available from 5 p.m. (Pacific) July 23 until 5 p.m. (Pacific) July 30.

WHERE:

The Webcast will be available online at: www.cadence.com/company/investor_relations

[eastunder]

Globes, Tel Aviv, Israel, Shmulik Shelah column: "Chip design is for the rich"

Monday , June 30, 2008 15:41ET

Jun 30, 2008 (Globes - McClatchy-Tribune Information Services via COMTEX) -- "I believe that within five years only two EDA companies will survive," said Magma Design Automation Rajeev Madhavan at the Silicom Ventures LLC international summit today. "We will therefore be one of these two big companies, or we will have been bought by one of them," he added.

This was Madhavan's first response to the $1.6 billion offer to purchase two weeks ago by electronic design automation (EDA) developer Cadence Design Systems Inc. (Nasdaq: CDNS) for Mentor Graphics Corporation (Nasdaq: MENT). Magma Design Automation Inc. (Nasdaq: LAVA) is the world's fourth largest EDA software developer. Magma's share has fallen 50 percent over the past year and it has a current market cap of $300 million, and could well become a takeover target for the EDA industry's number two company, Synopsis Inc. (Nasdaq: SNPS).

Madhavan talked extensively about the changes in the semiconductor industry and their effect on EDA vendors. He believes that the cost of designing 45-nanometer processors is now $50-100 million, which is why there are fewer start-ups in the industry than there were a decade ago, when he founded Magma.

Madhavan noted, "The industry has changed. If you are the manager of a start-up and think that you have a processor that can run much faster than what now exists, know that the market has changed. You need to differentiate yourselves, for example by integrating an architecture change in an existing processor. The complex design of a system on a chip is for the big companies."

Madhavan said that the significance of the change was the need for much more money in the semiconductor industry. "Chip design is for the rich. That's the truth. I believe that the transition of small companies to develop small architecture changes in processors rather than the entire processor must happen. Israeli and American start-ups must understand this in order to survive."

Madhavan concluded, "In a few years, hardware groups will be much smaller than software groups. We'll see software becoming easier to work with and more involved in the hardware side. Software and chip design from the hardware side will be one unit and not separate ones."

To see more of the Globes or to subscribe to the newspaper, go to
http://www.globes.co.il. Copyright (c) 2008, Globes, Tel Aviv, Israel Distributed by
McClatchy-Tribune Information Services. For reprints, email
[e-mail], call 800-374-7985 or 847-635-6550, send a fax to
847-635-6968, or write to The Permissions Group Inc., 1247 Milwaukee Ave., Suite 303,
Glenview, IL 60025, USA.

Shmulik Shelah
Copyright (C) 2008 Globes, Tel Aviv, Israel

**********************************************************************

As of Thursday, 06-26-2008 23:59, the latest Comtex SmarTrend® Alert,
an automated pattern recognition system, indicated a DOWNTREND on
12-17-2007 for LAVA @ $12.67.

For more information on SmarTrend, contact your market data
provider or go to www.mysmartrend.com

SmarTrend is a registered trademark of Comtex News Network, Inc.
Copyright © 2004-2008 Comtex News Network, Inc. All rights reserved.

[eastunder]

Mentor Graphics Retains Goldman Sachs and Merrill Lynch To Advise on Unsolicited Offer From Cadence Design Systems

Monday , June 30, 2008 09:00ET

WILSONVILLE, Ore., June 30 /PRNewswire-FirstCall/ -- Mentor Graphics Corporation (Nasdaq: MENT) today announced that its Board of Directors has retained Goldman Sachs and Merrill Lynch as financial advisors with respect to Cadence Design Systems, Inc.'s (Nasdaq: CDNS) unsolicited written proposal to acquire all outstanding shares of Mentor at a price of $16.00 per share. In addition, Latham & Watkins LLP is acting as legal advisor to Mentor Graphics.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $850 million and employs approximately 4,200 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

Contact:
Mike Buckley, Sabrina Guttman or Ashley Zandy
Brunswick Group - San Francisco
415-293-8461

Guy Potvin
Brunswick Group - New York
212-333-3810

SOURCE Mentor Graphics Corporation


--------------------------------------------------------------------------------

Contacts:

Mike Buckley
Sabrina Guttman
Ashley Zandy all of Brunswick Group - San Francisco

415-293-8461

Guy Potvin
Brunswick Group - New York
212-333-3810

[eastunder]

Cadence goes public with Mentor bid: $1.6 billion cash offer was rejected

Wednesday, June 18, 2008 09:45ET

Jun 18, 2008 (San Jose Mercury News - McClatchy-Tribune Information Services via COMTEX) -- After two months of quietly trying to buy Mentor Graphics for $1.6 billion, San Jose-based Cadence Design Systems on Tuesday went public with its unsolicited takeover bid in an effort to pressure the Oregon company into accepting its offer.

But in a statement, Mentor Chief Executive Officer Walden Rhines said his company still opposed combining the firms, which both make software to design computer chips for various products.

"We concluded that not only was the price insufficient to support a transaction but that the risks of not gaining regulatory approval were sufficiently high that the ability of the parties to consummate the transaction would be in jeopardy," Rhines said.

Analysts dubious

During a conference call, one analyst said the purchase price seemed too high. Another worried that because the companies have similar products, federal regulators might fear their combination would dominate the market and hinder competition.

Nonetheless, Cadence executives insisted they saw no significant regulatory hurdles to the merger. And they defended their $16 per-share cash offer, which represents a 30 percent premium over Mentor's closing stock price on Monday and a 59 percent premium over Mentor's price on May 2, when they first offered Mentor the deal.

"We believe the combination of Cadence and Mentor Graphics delivers significant benefits to both companies' shareholders

that are simply too compelling to ignore," Cadence Chief Financial Officer Kevin Palatnik said in a prepared statement.

Cadence's chief executive, Michael Fister, also sent Rhines a letter Tuesday saying he was disappointed Rhines wouldn't "meaningfully participate" in merger talks.

"It remains our preference to bring Cadence and Mentor Graphics together through a negotiated transaction," Fister's letter said. "However, given Mentor Graphics' refusal to engage in substantive discussions with us concerning our all-cash premium acquisition proposal and the importance of this transaction to both companies' respective shareholders, we have decided to publicly disclose our proposal."

The decision to go public with the $1.6 billion bid was meant to make sure Mentor's investors "are well aware" of the proposal, Fister said in an interview. The consequence of that for Mentor's executives, he added, "is I'm sure they'll have a conversation with their shareholders" about the proposed deal.

Fister said it was "too early to speculate" about whether Cadence would mount a hostile takeover by offering to buy stock directly from Mentor's shareholders.

'Real ugly'

Gary Smith, an electronics design analyst with Gary Smith EDA of Santa Clara, said joining the two companies didn't seem to make sense.

"They have almost matching product lines," he said. "All they're going to do is take customers away from each other."

Smith also pointed out that the semiconductor industry is going through one of its periodic phases to shrink computer chip components, which will require companies like Cadence to significantly rewrite their chip software. If Cadence buys Mentor, he said, it might not have enough money to invest in new software.

In a note to its clients Tuesday, investment bank RBC Capital Markets advised Cadence's shareholders to support the deal. But it predicted Mentor would fight a takeover and that "this could get real ugly soon."

The RBC note also said a Cadence-Mentor combination "would offer serious competitive threat to Synopsys" a Mountain View company whose software also helps design computer chips. As a result, it said, "we will not be surprised if Synopsys offers a counter bid" for Mentor.

Synopsys spokeswoman Yvette Huygen declined to comment about that.

Contact Steve Johnson at [e-mail] or [phone].

To see more of the San Jose Mercury News, or to subscribe to the newspaper, go to
http://www.mercurynews.com. Copyright (c) 2008, San Jose Mercury News, Calif.
Distributed by McClatchy-Tribune Information Services. For reprints, email
[e-mail], call 800-374-7985 or 847-635-6550, send a fax to
847-635-6968, or write to The Permissions Group Inc., 1247 Milwaukee Ave., Suite 303,
Glenview, IL 60025, USA.

Steve Johnson
Copyright (C) 2008 San Jose Mercury News, Calif.

[eastunder]

BRIEF: FAST FACTS ON CADENCE, MENTOR GRAPHICS

Wednesday, June 18, 2008 09:43ET

Jun 18, 2008 (San Jose Mercury News - McClatchy-Tribune Information Services via COMTEX) -- FAST FACTS ON CADENCE, MENTOR

Cadence Design Systems

Headquarters: San Jose

Founded: 1988

2007 revenue: $1.61 billion

2007 profit: $296.2 million

Number of employees: 5,100

Closing stock price Tuesday: down 75 cents to $10.84.

Mentor Graphics

Headquarters: Wilsonville, Ore.

Founded: 1981

2007 revenue: $879.7 million

2007 profit: $28.7 million

Number of employees: 4,200

Closing stock price Tuesday: up $2.65 to $14.98.

[eastunder]

Cadence presses Mentor with $1.6 billion bid

Tuesday , June 17, 2008 19:19ET

Jun 17, 2008 (San Jose Mercury News - McClatchy-Tribune Information Services via COMTEX) -- Hoping to persuade Mentor Graphics to reconsider its recent private overtures to merge, San Jose-based Cadence Design Systems today made public its $1.6 billion takeover bid for the Oregon company.

The company's $16 per share cash offer represents a 30 percent premium over Mentor Graphics' closing common stock price on Monday, according to Cadence executives. They said it also amounts to a 59 percent premium over Mentor's closing stock price on May 2, when Cadence first proposed buying Mentor for that price.

"We believe the combination of Cadence and Mentor Graphics delivers significant benefits to both companies' shareholders that are simply too compelling to ignore," Cadence Chief Financial Officer Kevin Palatnik said in a prepared statement.

Cadence also disclosed a letter from its Chief Executive Officer, Michael Fister, to Mentor's Chief Executive, Walden Rhines, in which Fister said he was disappointed in Rhines' failure to "meaningfully participate" in merger talks.

"It remains our preference to bring Cadence and Mentor Graphics together through a negotiated transaction," Fister's letter said. "However, given Mentor Graphics' refusal to engage in substantive discussions with us concerning our all-cash premium acquisition proposal and the importance of this transaction to both companies' respective shareholders, we have decided to publicly disclose our proposal. We believe there are clear and compelling advantages to a combination of Cadence

and Mentor Graphics."

Mentor executives were not immediately available for comment.

More technology news and opinion at www.siliconvalley.com

Contact Steve Johnson at [e-mail] or [phone].

To see more of the San Jose Mercury News, or to subscribe to the newspaper, go to
http://www.mercurynews.com. Copyright (c) 2008, San Jose Mercury News, Calif.
Distributed by McClatchy-Tribune Information Services. For reprints, email
[e-mail], call 800-374-7985 or 847-635-6550, send a fax to
847-635-6968, or write to The Permissions Group Inc., 1247 Milwaukee Ave., Suite 303,
Glenview, IL 60025, USA.

Steve Johnson
Copyright (C) 2008 San Jose Mercury News, Calif.

[eastunder]

Mentor Graphics Responds to Proposal from Cadence Design Systems

Tuesday , June 17, 2008 14:24ET

WILSONVILLE, Ore., Jun 17, 2008 (BUSINESS WIRE) -- Mentor Graphics Corporation (Nasdaq: MENT) today acknowledged receipt of an unsolicited proposal by Cadence Design Systems (Nasdaq: CDNS) to acquire Mentor Graphics at a price of $16.00 per share. Mentor Graphics confirmed that it previously rejected the proposal.

"As we recently indicated to Cadence, we reviewed Cadence's proposal and analyzed both the price proposed and the risks associated with obtaining antitrust approval for a combination between the companies," said Walden C. Rhines, chairman and CEO of Mentor Graphics. "Following this review, we concluded that not only was the price insufficient to support a transaction but that the risks of not gaining regulatory approval were sufficiently high that the ability of the parties to consummate the transaction would be in jeopardy. For these and other reasons, our Board unanimously rejected the proposal."

[eastunder]

Cadence Proposes to Acquire Mentor Graphics for $16.00 per Share in Cash

Tuesday , June 17, 2008 07:00ET



SAN JOSE, CA -- (MARKET WIRE) -- 06/17/08 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced that it submitted a proposal to the Board of Directors of Mentor Graphics Corporation (NASDAQ: MENT) to acquire Mentor Graphics for $16.00 per share in cash. Cadence's all-cash proposal, which is not subject to any financing condition, represents a 30% premium over the closing price of Mentor Graphics common stock on June 16, 2008, the last trading day prior to public disclosure of Cadence's proposal, a 59% premium over the closing price of Mentor Graphics common stock on May 2, 2008, when Cadence presented the terms of the proposal to Mentor Graphics, and a 46% premium over Mentor Graphics' average closing price for the past 30 trading days. The transaction price represents a total enterprise value of $1.6 billion on a fully diluted basis, which reflects Mentor Graphics' net debt of $69 million.

"A combined Cadence-Mentor will offer customers a broader and more fully integrated product and technology portfolio in a timeframe that better enables them to address urgent and complex challenges associated with their next-generation product development," said Michael J. Fister, president and chief executive officer of Cadence. "Together, we will accelerate the rate and efficiency of customers' innovation by making it possible for them to develop products that better meet end user needs."

"We believe the combination of Cadence and Mentor Graphics delivers significant benefits to both companies' shareholders that are simply too compelling to ignore," said Kevin S. Palatnik, senior vice president and chief financial officer of Cadence. "Our $16.00 per share all-cash proposal provides Mentor Graphics shareholders with a substantial cash premium for their investment in Mentor Graphics. It remains our strong preference to work cooperatively with Mentor Graphics, and to immediately commence discussions with Mentor Graphics regarding our proposal."

Cadence's proposal is subject to the negotiation of a mutually agreeable merger agreement, the completion of certain limited and confirmatory due diligence, and the satisfaction of other customary conditions, including receipt of regulatory approvals.

Deutsche Bank Securities Inc. is acting as financial advisor to Cadence and Davis Polk & Wardwell is acting as legal counsel.

Below is the text of the letter that was sent earlier today to the Board of Directors of Mentor Graphics, in care of Walden C. Rhines, Chairman and Chief Executive Officer of Mentor Graphics:

June 17, 2008


The Board of Directors of Mentor Graphics Corporation
c/o Walden C. Rhines
Chairman of the Board of Directors
and Chief Executive Officer
Mentor Graphics Corporation
8005 S.W. Boeckman Road
Wilsonville, OR 97070


Dear Wally:

Over the last two months, we have sought to engage you and your Board of Directors in discussions regarding our proposal to combine Cadence Design Systems, Inc. and Mentor Graphics Corporation. We are disappointed that, despite our best efforts, you have thus far been unwilling to meaningfully participate in such discussions.

As you will recall, you and I first spoke about combining Cadence and Mentor Graphics on April 16, 2008. On May 2, 2008, Bill Porter and I met with you and Greg Hinckley in Portland where we presented the terms of our proposal to acquire Mentor Graphics for $16.00 per share in cash.

Following the May 2nd meeting, we repeatedly attempted to bring the Cadence and Mentor Graphics leadership teams together to discuss our proposal. On May 23, 2008, however, you informed us that, even without any substantive discussion with us or negotiation of our proposal, Mentor Graphics concluded that it did not wish to pursue discussions with us given Mentor Graphics' desire to stay independent.

It remains our preference to bring Cadence and Mentor Graphics together through a negotiated transaction. However, given Mentor Graphics' refusal to engage in substantive discussions with us concerning our all-cash premium acquisition proposal and the importance of this transaction to both companies' respective shareholders, we have decided to publicly disclose our proposal. We believe there are clear and compelling advantages to a combination of Cadence and Mentor Graphics.

As Bill and I explained to you on May 2, based upon our knowledge of Mentor Graphics from currently available public information, Cadence is prepared to acquire Mentor Graphics for $16.00 per share in cash. Our proposal is not subject to any financing condition. This proposal is a full and fair price and provides an attractive opportunity for your shareholders to realize, with certainty, significant value for their investment in Mentor Graphics. This price represents a 30% premium over the closing price of Mentor Graphics common stock on June 16, 2008, the last trading day prior to public disclosure of our proposal, a 59% premium over the closing price of Mentor Graphics common stock on May 2, when we presented the terms of our proposal, and a 46% premium over Mentor Graphics' average closing price for the past 30 trading days.

We believe that a combined Cadence-Mentor will provide customers a broader and more fully integrated product and technology portfolio in a timeframe that better enables them to address urgent and complex challenges associated with their next-generation product development. From increasing complexity to stringent cost targets, developers must optimize and prioritize their efforts across the entire spectrum of specification, architecture, design, implementation, verification, and manufacturing.

Combining Cadence and Mentor Graphics and aligning the creative talents of our respective hard-working and innovative employees will deliver more comprehensive cutting-edge solutions and an entirely new level of customer experience and satisfaction. Together we can accelerate the rate and efficiency of customers' innovation by making it possible for them to develop products that better meet end user needs.

Our proposal is subject to the negotiation of a mutually acceptable merger agreement and completion of certain limited and confirmatory due diligence, which we believe we will be able to complete expeditiously, as well as satisfaction of other customary conditions, including receipt of regulatory approvals. We and our advisors have carefully analyzed the combination of Cadence and Mentor Graphics and are confident that the proposed transaction will receive the necessary regulatory approvals.

We strongly believe that a combination of Cadence and Mentor Graphics will create significant value for both companies' respective shareholders and customers. Our leadership team and advisors remain prepared to meet with you and your advisors at your earliest convenience to conduct the necessary due diligence and negotiate a merger agreement. I am confident that the Cadence and Mentor Graphics teams working together can make this transaction a success.

The Board of Directors of Cadence unanimously supports this proposal and the combination of Cadence and Mentor Graphics. We expect you and the Mentor Graphics Board to give this proposal serious consideration. I look forward to hearing from you soon.

Sincerely yours,

/s/ Michael J. Fister


Michael J. Fister
President and Chief Executive Officer

[eastunder]

Cadence Enhances RF Verification With High-Performance 'Turbo' Technology and Comprehensive Electromagnetic Analysis

Monday , June 16, 2008 08:00ET



SAN JOSE, CA -- (MARKET WIRE) -- 06/16/08 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today introduced a new simulation technology to address the challenges of verifying wireless integrated circuits implemented in advanced CMOS process nodes. Cadence has added the "turbo" technology it recently brought to the Virtuoso® Spectre® Circuit Simulator to its RF analysis. The result is performance improvements of two to five times -- sometimes greater -- for analysis and verification of large RF circuits targeting advanced CMOS process nodes, and with no degradation in accuracy.

"As developers and IP providers of some of the most advanced RFIC designs, we have found that Virtuoso Spectre with turbo technology delivered six times performance improvement for RF analysis of some of our most complex RF analog circuits, without any compromise of accuracy," said Tom Riley, CTO at Kaben Wireless Silicon. "These sampled-RF circuits have enough moving parts to be a convergence challenge for any simulator. The new turbo technology is easy to learn and use for someone familiar with using the Virtuoso Spectre simulator. "

"We design high-performance communication front-ends for wireless, wired, and fiber optics physical layers in advanced CMOS process nodes," said Emad Afifi, vice president of Engineering at Ensphere Solutions, Inc. "When we ran Spectre with turbo technology and accurate parasitic reduction on some of our leading-edge analog and RF circuits, simulation time was reduced by more than six times without any accuracy degradation. We expect this new technology to improve the productivity of our engineers and reduce our time to market."

This technology complements a complete manufacturability-aware solution from Cadence for design, implementation and verification of RF integrated circuits (RFICs). Based on the Virtuoso custom design platform, this solution enables designers to deal with the challenge of integrating RF with analog/mixed-signal baseband, and the emerging need for RFIC-focused electromagnetic analysis. It improves time to market and overall design costs through faster and more accurate verification that reduces design turnaround time and expensive silicon respins.

The complete solution includes the Cadence Virtuoso RF Designer, which brings a full-wave fast planar electromagnetic (EM) field solver to the RF/wireless designer's desktop. Virtuoso RF Designer offers designers advanced verification capabilities for faster electromagnetic analysis of complex structures and geometries -- all within a single design flow, accelerating chip finishing and verification. Virtuoso RF Designer integrates seamlessly into the Virtuoso front-end and leverages Cadence's patented electromagnetic analysis technology to accelerate and accommodate large designs found in today's RFICs and System-on-Chip (SoC).

The Cadence RFIC solution provides an interactive link between system design and circuit design by integrating with Simulink from The MathWorks.

"RF system designers use MATLAB and Simulink for system design and refining specifications for each RF block in the context of the system," said Ken Karnofsky, director of signal processing and communications marketing, The MathWorks. "Because Cadence integrated Virtuoso Multi-Mode Simulation with MATLAB and Simulink, RFIC designers may insert their block schematics and post-layout netlist directly in the system-level block diagram and use co-simulation to verify that the implementation meets system-level specifications."

In addition, Cadence has developed a toolbox for MATLAB that allows designers to access their simulation results in MATLAB for advanced visualization and post-processing.

"RFIC circuits are critical and challenging components of today's advanced mixed-signal SoCs," said Sandeep Mehndiratta, Virtuoso product marketing group director at Cadence. "Cadence continues to enhance its comprehensive RF solution with leading-edge technologies that enable designers to tackle these challenging designs. With the new turbo-powered Spectre RF and the Virtuoso RF Designer, we are providing our customers with technology that can help them meet their first-pass silicon success and time-to-market goals."

Cadence will demonstrate its latest RF technology at the International Microwave Symposium, June 15-20 in Atlanta.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, Spectre and Virtuoso are registered trademarks, and the Cadence logo is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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--------------------------------------------------------------------------------For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226
[e-mail]

Source: Cadence Design Systems, Inc.

[eastunder]

Cadence Collaborates With UMC to Deliver 65NM CPF-Based Low-Power Reference Design Flow

Monday , June 09, 2008 08:00ET

SAN JOSE, CA and HSINCHU, TAIWAN -- (MARKET WIRE) -- 06/09/08 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and UMC (NYSE: UMC) (TSE: 2303), a leading global semiconductor foundry, today announced the availability of a Common Power Format (CPF)-based low-power reference design flow targeted to the UMC 65-nanometer process. This reference flow enables customers to achieve optimal 65-nanometer low-power designs when used with UMC's Low Power Kit, which includes CPF-enabled libraries and other intellectual property.

This 65-nanometer low-power reference design flow uses UMC's "Leon" test chip as the reference design. Leon is an open source 32-bit RISC microprocessor core with other complex elements including SRAM. The Leon chip was partitioned into multiple voltage domains using the Cadence Low-Power Solution for design, verification, implementation and analysis. As proven with the Leon test chip, the combination of the 65-nanometer reference design flow and the UMC Low Power Kit enables increased productivity while managing design complexity, shortening time-to-market and reducing manufacturing risk.

The UMC 65-nanometer low-power reference design flow highlights key capabilities of the Cadence Low-Power Solution, including Cadence Incisive® Unified Simulator for gate-level low-power simulation; Cadence Encounter® RTL Compiler for synthesis, low-power and DFT cell insertion; Encounter Conformal Low Power for equivalence checking and low power design implementation checking; Encounter Test for ATPG; SoC Encounter RTL-to-GDSII system for floorplanning, powerplan and place-and-route; Encounter Timing System for timing and SI signoff; Cadence QRC Extraction; VoltageStorm® PE for static power and IR analysis; and VoltageStorm DG and Virtuoso® UltraSim for dynamic analysis of current surge at power up. In addition, UMC's Low Power Kit, including its CPF-enabled library, was validated as part of the reference design flow development.

"We are working closely with Cadence to address complex design issues that face designers at 65 nanometers, while enabling faster time to volume through an integrated low-power solution," said Darsun Tsien, UMC's vice president of design methodology. "Through our ongoing collaboration with Cadence, we are able to provide designers with validated low-power technologies to manage power concerns and meet aggressive time-to-market goals."

"This CPF-based flow, the result of a joint effort between Cadence and UMC, accelerates implementation of low-power designs," said Chi-Ping Hsu, corporate vice president of IC Digital and Power Forward at Cadence. "The combination of UMC process technology and the Cadence Low-Power Solution provides our mutual customers with the ability to realize their aggressive project goals while preserving low-power intent throughout the design process."

Availability

This reference flow package includes design resources, implementation scripts, an application note and a comprehensive workbook. This 65-nanometer Low Power reference design flow is slated for availability in July 2008 through UMC sales.

About UMC

UMC (NYSE: UMC) (TSE: 2303) is a leading global semiconductor foundry that manufactures advanced system-on-chip (SoC) designs for applications spanning every major sector of the IC industry. UMC's SoC Solution Foundry strategy is based on the strength of the company's advanced technologies, which include production proven 90nm, 65nm, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 13,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com

Cadence, Encounter, Incisive, Conformal, Virtuoso and VoltageStorm are registered trademarks, and the Cadence logo and SoC Encounter are trademarks, of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.





Where ever you go...go with your heart.

[eastunder]

Cadence Collaborates With Common Platform and Arm to Deliver 45-NM RTL-to-GDSII Reference Flow

Monday , June 09, 2008 08:00ET



SAN JOSE, CA -- (MARKET WIRE) -- 06/09/08 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced the 45-nanometer reference flow targeting Common Platform(TM) technology available for general release in July 2008. Cadence® and the Common Platform technology companies, comprised of IBM, Chartered Semiconductor Manufacturing and Samsung Electronics, collaborated to develop this RTL to GDSII 45-nanometer flow to address advanced node design requirements. This reference flow is based on the Common Power Format (CPF)-enabled Cadence Low-Power Solution and also includes key Design For Manufacturing (DFM) technology from Cadence. This joint optimization is expected to provide significant power savings, yield enhancement and time-to-market advantages for customers designing high-volume consumer, communications and mobile electronic devices targeted to the Common Platform technology 45-nanometer process.

This reference flow uses the 45-nanometer ARM® Physical IP low-power libraries and enables designers to perform design exploration and physical prototyping using different CPF files and a single golden RTL, allowing low-power architecture optimization. It employs the advanced power management capabilities in the Cadence Low-Power Solution -- including power shut off prototyping, power domain-aware placement, clock tree synthesis and routing, multi-mode and multi-corner analysis and optimization -- to deliver higher productivity and the utmost in power reduction for advanced designs.

"Consumer demand for portable products is accelerating as longer, reliable connectivity becomes a necessity. This is driving an increasing demand for designs with optimized power management schemes," said Tom Lantzsch, vice president of marketing, Physical IP Division at ARM. "Working with Cadence, ARM is aggressively pursuing the enablement of our mutual customers to develop industry leading embedded products. As part of this collaboration, we are now offering CPF views with the ARM Physical IP libraries. The 45-nm ARM Physical IP with Power Management Kit targeted to the Common Platform technology is the latest evolution of our commitment to CPF-based reference flow collaboration with Cadence."

As part of this 45-nm reference flow, Cadence also provides an integrated suite of foundry certified, model-based DFM analysis and implementation technologies for silicon-accurate analysis and physical design optimization. These technologies offer silicon-accurate modeling and optimization of critical manufacturing variations that can be used to improve both performance and physical yield results during design implementation. At advanced process nodes, traditional design flows no longer provide accurate predictability, forcing designers to either guardband their designs excessively or risk manufacturability problems. By modeling key manufacturing processes within the implementation flow and optimizing early, designers reduce overall turnaround time and improve their confidence that the chip will work as intended.

This 45-nm reference flow is built around the Cadence Encounter® platform for DFM-aware prevention, detection and optimization. It has been demonstrated within the Common Platform that features which may result in yield-limiting issues in lithography are quickly and accurately identified using the Cadence Litho Physical Analyzer. These model-based DFM results are used to drive the Cadence SoC Encounter(TM) RTL-to-GDSII system -- for prevention and manufacturing-aware design closure, and Cadence Chip Optimizer -- for incremental space-based interconnect optimization and final manufacturability optimization. Cadence QRC Extractor provides the essential modeling link between the physical, manufacturing and electrical domains. DFM effects can be extracted and timing impact can be back-annotated to the physical implementation stage for accurate model-based timing optimization.

The Cadence 45nm reference flow for the Common Platform, provides capabilities which help bring manufacturing predictability back to the designer. This drives result in higher quality silicon with better time-to-volume.

"Low-power design and design for manufacturability are key factors for customers when choosing to adopt the 45-nm Common Platform technology," said Mark Ireland, vice president, Common Platform, at IBM. "In order to address these issues, the Common Platform companies worked with Cadence engineers to deliver this 45-nm reference flow. The result is an innovative yield-aware solution with seamless implementation of power intent using CPF."

"This collaboration between Cadence and the Common Platform provides a 45-nm silicon-aware reference flow that can be quickly deployed by engineering teams seeking predictable design flows that deliver superior quality of silicon," said Chi-Ping Hsu, corporate vice president of Digital IC and Power Forward at Cadence. "The combination of the Cadence Low-Power Solution and DFM technologies, and the Common Platform 45-nm process technology, provide designers a complete solution to address the complexities and interdependent needs of low power and advanced process technology."

The Advanced node capabilities in the Cadence 45nm Reference Flow provide "what you design is what you get" (WYDIWYG) modeling, advanced low power techniques, and optimization of critical manufacturing variations that can be used to improve results of the design phase. This helps to result in faster, lower power and more accurate silicon.

Availability

The 45-nanometer advanced low-power, yield-optimization reference flow will be available in July by sending an email request to [e-mail]. This reference flow kit contains a reference design, documentation and scripts to run the reference flow.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, Encounter, Conformal and VoltageStorm are registered trademarks, and the Cadence logo and SoC Encounter are trademarks, of Cadence Design Systems, Inc. in the U.S. and other countries. All other trademarks are the property of their respective owners.

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--------------------------------------------------------------------------------For more information, please contact:
Dan Holden
Cadence Design Systems, Inc.
Direct: 408-944-7457
[e-mail]

Source: Cadence Design Systems, Inc.

[eastunder]

Calypto Delivers Optimized Power Flow with Cadence Design Systems

Thursday , May 29, 2008 11:00ET

SANTA CLARA, Calif., May 29, 2008 (BUSINESS WIRE) -- Calypto(TM) Design Systems Inc., the leader in sequential analysis technology, today announced the availability of an RTL power optimization flow to integrate Calypto's PowerPro CG product with the Encounter(R) RTL Compiler from Cadence Design Systems, Inc. The integrated flow provides an automated, single-pass sequential analysis capability that produces the lowest power implementation while still meeting design constraints.

By using Encounter RTL Compiler's multi-objective synthesis and PowerPro CG's sequential analysis capability, the integrated flow optimizes sequential clock gating by using accurate timing information in the power/performance trade-off analysis. The collaborative effort has resulted in a seamless design flow that generates RTL code that reduces power in system-on-chip designs. In addition, the collaboration has identified new constructs to be added to the Si2 Common Power Format (CPF) standard that will be beneficial for system-level design flows.

"The integration of PowerPro CG with Encounter RTL Compiler provides our mutual customers with automated sequential RTL clock gating within their existing synthesis environments," says Nimish Modi, corporate vice president of Front-End Design R&D at Cadence. "This provides customers with additional power optimization while not impacting the performance of their designs."

Calypto's PowerPro CG which is based on patented Sequential Analysis Technology reduces power by up to 60%. PowerPro CG evaluates circuit behavior across multiple clock cycles to identify and insert sequential clock gating enable logic into RTL designs while maintaining all user defined pragmas and comments. PowerPro CG consistently produces better results in significantly less time than manual clock gating.

The Cadence Encounter(R) RTL Compiler, a key technology in the Cadence(R) Encounter digital IC design platform and a component of the Cadence Logic Design Team Solution, delivers production-proven global synthesis for faster, smaller, and low-power chips in less time. With its unique set of patented global-focus algorithms, combined with physically-aware optimization and analysis, Encounter RTL Compiler cuts design time while ensuring the highest quality of silicon.

"We are delighted to work with Cadence and the Power Forward Initiative to deliver this industry leading RTL power optimization flow," remarks Tom Sandoval, Calypto's chief executive officer (CEO). "We will continue to work with the Power Forward Initiative to define new ways to improve low-power design flows that produce the lowest power SoC's possible."

CPF, a Si2 standard format, is used for specifying power-saving techniques early in the design process, enabling sharing and reuse of low-power intelligence throughout the design flow. The Cadence Low-Power Solution is the industry's first complete flow that integrates logic design, verification, and implementation with the Common Power Format.

About Power Forward Initiative

The Power Forward Initiative, which has more than 25 member companies, is an industry initiative sponsored by Cadence and has the goal of enabling the design and production of more power-efficient electronic devices. The initiative includes companies representing a broad cross section of the design chain including system, semiconductor, foundry, IP, EDA, ASIC and design services companies. CPF was contributed by Cadence to the Si2 Low-Power Coalition in December 2006 and CPF 1.0 is now available as an Si2 standard to the industry at large. The Initiative has also published A Practical Guide to Low-Power Design -- User experience with CPF which is aimed at educating the broad design marketplace in utilizing advanced low-power design techniques. The Guide is available free of charge at www.powerforward.org.

About Calypto

Founded in 2002, Calypto Design Systems, Inc. empowers designers to create high-quality, low-power electronic systems by providing best-in-class power optimization and functional verification software, based on its patented sequential analysis technology. Calypto, whose customers include Fortune 500 companies worldwide, is a member of the Cadence Connections program, the IEEE-SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program and the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America. Corporate Headquarters is located at: 2933 Bunker Hill Lane, Suite 202, Santa Clara, Calif. 95054. Telephone: [phone]. More information can be found at: www.calypto.com.

Calypto, PowerPro, SLEC and Enabling ESL are trademarks of Calypto Design Systems Inc. Other products and company names may be trademarks or registered trademarks of their respective companies.

SOURCE: Calypto Design Systems Inc.

Public Relations for Calypto Design Systems
Nanette Collins, 617-437-1822
[e-mail]

Copyright Business Wire 2008

[eastunder]

Lawd...I'm bored.

Get out the paddles...STAT!...Code blue...we've gone flat line.

[eastunder]

Cadence Announces First Quarter 2008 Financial Results Webcast

WHO:

Cadence Design Systems, Inc. (NASDAQ: CDNS) to announce first quarter 2008 financial results via Webcast.

WHAT:

You are invited to attend the first quarter 2008 financial results audio Webcast. Participating on the Webcast will be Mike Fister, president and chief executive officer, and Bill Porter, executive vice president and chief financial officer.

WHEN:

The Webcast will begin Wednesday, April 23, 2008 at 2 p.m. (Pacific)/5 p.m. (Eastern). An archive of the Webcast will be available from 5 p.m. (Pacific) April 23 until 5 p.m. (Pacific) April 30.

WHERE:

The Webcast will be available online at: www.cadence.com/company/investor_relations

[eastunder]

CDNS: Short Interest DN 7.6% to 16.5M at the End of Mar 2008

According to new short interest data from NASDAQ, short interest for Cadence Designs Systems, Incorporated (NasdaqNM: CDNS) DECREASED 7.6% to 16,512,058 shares as reported at month-end March, 2008.

SYMBOL CDNS
MID MARCH 17,871,802
END MARCH 16,512,058
CHANGE -1,359,744
%CHANGE 7.61%
DAYS/COVER 5

Based on CDNS's 20-day average daily share volume of 3,909,410, it would require approximately 5 day(s) of buying to cover this short interest.

[eastunder]

Cadence Design Systems Announces Authorization of $500 Million Stock Repurchase

Wednesday, February 20, 2008 16:04ET

SAN JOSE, CA -- (MARKET WIRE) -- 02/20/08 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its Board of Directors has approved a stock repurchase program that authorizes Cadence to repurchase its common stock with a value of up to $500 million in the aggregate, effective immediately. This is in addition to the approximately $8.36 million remaining from Cadence's previous stock repurchase authorization.

Share repurchases under this program may be made in the open market or in privately negotiated transactions. The timing and actual number of shares repurchased will depend on a variety of factors including price, corporate and regulatory requirements and other market conditions.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,300 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence is a registered trademark, and the Cadence logo is a trademark, of Cadence in the United States and other countries. All other trademarks are the property of their respective owners.

--------------------------------------------------------------------------------For more information, please contact:
Jennifer Jordan
Investors and Shareholders
Cadence Design Systems, Inc.
408.944.7100
[e-mail]

Adolph Hunter
Media and Industry Analysts
Cadence Design Systems, Inc.
408.914.6016
[e-mail]

Source: Cadence Design Systems, Inc.

[eastunder]

re:CDNS laying off 84 employees on Feb. 4 at 2655 Seely Ave. in San Jose.

Knobias has employee count at 5200 employees

[eastunder]

From 4 info:

Insider Trading Report: Cadence Design Systems Inc (CDNS)

Tuesday , February 12, 2008 06:08ET

Feb 12, 2008 (M2 PRESSWIRE via COMTEX) -- As the stock was trading near its 52-week low, Tan Lip Bu, Director at Cadence Design Systems Inc (CDNS) has reported buying $53.45K today.Over the last four weeks insiders at Cadence Design Systems Inc (CDNS) have bought more than $97.31K:

- Swainson John A, Director: bought $43.86K increasing total holdings by 400%

- Tan Lip Bu, Director: bought $53.45K increasing total holdings by 83%

For a current, real-time summary of CDNS insider activity, visit http://www.form4oracle.com/company?cik=0000813672&ticker=CDNS About Form4Oracle

Form4Oracle, LLC specializes in distributing insider trading information published by the SEC, making it accessible and actionable for all types of investors.

[eastunder]

Lets review that again... :)

[Lakers_w]

Ray Bingham, managing director with General Atlantic PE firm, CoB of CDNS
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=206104744

Freescale's issues, coupled by the slowing economy, have contributed to a "cooling" down period for private equity deals in the semiconductor industry, said Ray Bingham, managing director with General Atlantic LLC, a global growth equity firm. Bingham is also executive chairman of Cadence Design Systems Inc. and sits on the boards of STMicroelectronics and others.

"For Freescale, it's a challenging time," Bingham, a former board member of Freescale. He was on the board up until Freescale became a private company. He hasn't served on the board since Dec. 1, 2006.

Bingham, who predicted that private equity deals would pick up when the economy improves, also defended such transactions. Contrary to popular belief, there is accountability and the ability to upgrade one's management team in a private equity deal, he said.

[Lakers_w]

CDNS laying off 84 employees on Feb. 4 at 2655 Seely Ave. in San Jose.
http://messages.finance.yahoo.com/Stocks_%28A_to_Z%29/Stocks_C/threadview?m=tm&bn=3282&tid=14222&mid=14222&tof=1&frt=2

[Lakers_w]

Dir. Swainson John A acquired 4K shrs @$10.9648 2/4/08
http://messages.finance.yahoo.com/Stocks_%28A_to_Z%29/Stocks_C/threadview?m=tm&bn=3282&tid=14213&mid=14213&tof=3&frt=2

[Lakers_w]

SC 13G FRANKLIN RESOURCES owns 26,827,429 shrs, 10%
http://messages.finance.yahoo.com/Stocks_%28A_to_Z%29/Stocks_C/threadview?m=tm&bn=3282&tid=14214&mid=14214&tof=2&frt=2

[Lakers_w]

CDNS-funded Lorentz Solution's PeakView Electromagnetic Simulation Qualified by TSMC
http://messages.finance.yahoo.com/Stocks_%28A_to_Z%29/Stocks_C/threadview?m=tm&bn=3282&tid=14215&mid=14215&tof=1&frt=2

[eastunder]

CDNS: Deutsche Bank Cuts to Hold from Buy

Thursday , January 31, 2008 13:55ET

Issuer: Cadence Designs Systems, Incorporated (NasdaqNM: CDNS)

Analyst Firm: Deutsche Bank

Ratings Action: DOWNGRADE

Current Rating: Hold (from Buy)








This rating information was reported by TheFlyOnTheWall.

[eastunder]

[eastunder]

and this morning it's even more lovely. :(

Thursday , January 31, 2008 10:19ET

By Staff Reporter
NEW YORK, Jan 31, 2008 (AP via COMTEX) -- Shares of Cadence Design Systems Inc. plunged in premarket electronic trading Thursday after the semiconductor manufacturing equipment maker sharply cut its outlook to below Wall Street expectations.

Late Wednesday, the San Jose, Calif., company cut its forecasts for both the first quarter and full year.

The move prompted a downgrade to "Underweight," or "Sell," from JPMorgan analyst Sterling Auty, who previously had a "Neutral" rating on the shares. It was the second downgrade from the analyst on Cadence in as many weeks. Auty said last week's cut was related to concerns about slowing research and development spending and larger issues related to slowing consumer spending on electronics. The analyst said the company's 2008 guidance for declining revenue and earnings "is well below even our recently cut numbers," and predicted the stock will have a "tough time performing" even if it bottoms out in Thursday's session.

Cadence shares dropped $3.45, or 22.8 percent, to $11.71 premarket. If the decline persists when the market opens, the stock would open below its annual low of $13.51, hit last week. Shares closed Wednesday at $15.16, 39 percent off their annual high, reached in June.

[eastunder]

getting torched in after hours. Down to 11.80 on horrific guidance

Cadence Design 4Q adj EPS in-line with TF avg est for 46c/share

Wednesday, January 30, 2008 17:49ET

By Staff Reporter
NEW YORK, Jan 31, 2008 (Thomson Financial via COMTEX) -- Cadence Design Systems Inc. late Wednesday said fourth-quarter adjusted income rose to $133 million, or 46 cents a share, from $115.8 million, or 38 cents a share, in the same period last year. Earnings were in-line with the mean estimate of analysts polled by Thomson Financial.

Fourth-quarter sales increased 6% to $457.9 million from $431 million in last year's comparable period, missing analysts' consensus view for sales of $470 million.

The electronic design company provided first-quarter guidance for adjusted earnings between 3 cents and 5 cents a share and for sales between $280 million and $290 million.

In fiscal 2008, it anticipates adjusted earnings between $1.11 and $1.19 a share and sales of between $1.49 billion and $1.54 billion.

Shares of the San Jose, Calif.-based company closed the regular session at $15.16. Melinda Peer mp/gm