CAST Releases MPEG-4 and JPEG 2000 IP Cores
By Mark Long -- e-inSITE, 1/27/2003
CAST, Inc. has announced the addition of new MPEG-4 video encoding and JPEG 2000 image decoding cores to the company's line of general purpose IP (gpIP) for electronic design applications. The new cores are available immediately for synthesis to ASICs or optimized for various FPGAs.
The company reports that its new CAST MPEG-4 core has been designed to handle the real-time encoding of full-screen video in under 50,000 ASIC gates. The offering is targeted at applications ranging from high-quality video conferencing to remote streaming of DVD-quality movies.
The CAST MPEG-4 core supports MPEG Advanced Simple Profile Levels 0 to 5 while handling resolutions as large as 704 x 576 at the same 30 fps rate. The MPEG-4 core also operates efficiently, requiring a clock rate of just eight times the raw pixel rate. The operating rate needed for videoconferencing (176 x 144 screen at 15 fps) is therefore just 3 MHz, or for VGA video (640 x 480 at 30 fps) only 74 MHz.
The CAST MPEG-4, which is ready for integration in an SoC or board, will work with any microprocessor, which will only need to supervise the encoding process and perform ancillary tasks such as bit rate control. The core also requires external memory for a frame buffer; a single 16 or 64 Mbit SDRAM with a 16-bit wide data bus is sufficient.
The CAST JPEG2K_D core has been designed for hardware acceleration applications for the new JPEG 2000 image processing standard. According to the company, the new core can decode a 5 Megapixel camera image in half a second, or standard definition TV (720 x 480 pixels) at 30 frames per second. In addition, the core offers a variety of implementation options and programmability features that will allow developers to tailor its processing abilities, size, and power consumption to meet the specific requirements of individual devices, applications, and systems, claims CAST.
Designers can tune the core's architecture during synthesis in support of larger or smaller image processing sizes or to control power/speed trade-off factors such as 2D-DWT filter types (5/3 or 9/7 or both) or the number of Entropy Encoding Units. Programmable settings are also available to allow designers to set the size and pixel depth of input images, number of 2D-DWT levels, or the code block size (32x32 or 64x64).
