United States Patent 7,570,689
Li , et al. August 4, 2009
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Advanced receiver with sliding window block linear equalizer
Abstract
A receiver or an integrated circuit (IC) incorporated therein includes a fast Fourier transform (FFT)-based (or hybrid FFT-based) sliding window block level equalizer (BLE) for generating equalized samples. The BLE includes a noise power estimator, first and second channel estimators, an FFT-based chip level equalizer (CLEQ) and a channel monitor unit. The noise power estimator generates a noise power estimate based on two diverse sample data streams. The channel estimators generate respective channel estimates based on the sample data streams. The channel monitor unit generates a first channel monitor signal including truncated channel estimate vectors based on the channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors. The FFT-based CLEQ generates the equalized samples based on the noise power estimate, one-block samples of the first and second sample data streams, the channel estimates and the monitor signals.
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Inventors: Li; Bin (Ronkonkoma, NY), DiFazio; Robert A. (Greenlawn, NY), Pan; Jung-Lin (Selden, NY), Reznik; Alexander (Titusville, NJ), Kaewell, Jr.; John David (Jamison, PA), Becker; Peter Edward (Coatesville, PA)
Assignee: InterDigital Technology Corporation (Wilmington, DE)
Appl. No.: 11/238,318
Filed: September 29, 2005
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Related U.S. Patent Documents
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Application Number Filing Date Patent Number Issue Date
60696922 Jul., 2005
60652790 Feb., 2005
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Current U.S. Class: 375/229 ; 375/240.02; 375/297
Current International Class: H04L 25/49 (20060101); H03H 7/30 (20060101); H04L 27/04 (20060101)
Field of Search: 375/229-236,240.02-240.07,297,312
