Intel Corp (INTC)

[ibc]

Intel and IBM to lay out 14nm FinFET strategies on competing substrates at IEDM 2014
http://electroiq.com/blog/2014/10/intel-and-ibm-lay-out-14nm-finfet-strategies-on-competing-substrates-at-iedm-2014/

Among the technical features Intel will discuss at the IEDM are: a novel doping technique to prevent current leakage under the fins and to maintain very low doped fins, resulting in improvement in variation; two levels of air-gap-insulated interconnects (electrical connections) at ultra-narrow 80 and 160nm minimum pitches, yielding a 17% reduction in capacitance delays; eight layers of 52nm pitch interconnects embedded in low-k dielectrics; an embedded 140Mb SRAM memory with a tiny cell size of 0.0588µm2; and saturated drive currents significantly higher than for Intel’s 22nm first-generation FinFETs (improvements of 15% and 41% for NMOS and PMOS transistors, respectively). The transistors operate with a supply voltage of only 0.7 Volts.
The researchers also will discuss how aggressive design rules enabled the production of very high aspect ratio rectangular fins (8nm wide and 42nm high) at unprecedented levels of uniformity.

IBM, meanwhile, will describe a very different approach to 14nm FinFET transistors. The IBM devices are made not from a standard bulk silicon substrate but from an insulating substrate known as SOI, a more expensive material but one which simplifies manufacturing in terms of device isolation. These devices are more than 35% faster than IBM’s 22nm planar (i.e. standard, non-FinFET) transistors, with an operating voltage of just 0.8 volts.

The IBM technology features what may be the smallest, densest embedded DRAM memory ever demonstrated (a cell size of just 0.0174µm2) for high-speed performance in a fully integrated process flow. IBM also designed an elegant way to make the technology suitable for both low-power and high-speed applications, using a unique dual-workfunction process that optimizes the threshold voltages of both NMOS and PMOS transistors without any mobility degradation in the channel.

Because the technology is envisioned for use in system-on-a-chip (SoC) applications ranging from video game consoles to enterprise-level corporate data centers, the IBM design also features a record 15 levels of copper interconnect to give circuit designers more freedom that ever before to distribute power and clock signals efficiently across an entire SoC chip, which may be as large as 600mm2.