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Re: muzohub post# 135865

Wednesday, 08/20/2014 6:50:37 AM

Wednesday, August 20, 2014 6:50:37 AM

Post# of 151628

DesignWare USB femtoPHYs are proven in customer silicon on 28-nm and 14-nm FinFET processes interesting, no?


Indeed. Funny, I have recently been reading this white paper from Synopsys about the design challenges involved while porting their existing USB IP to 14nm. It basically comes down to a redesign of the output-bridge (I suppose the only analog design of that IP). That already involves quite some effort for a redesign and especially simulation. Guess how difficult it is to redesign more complex analog circuitry, like ultra fast A/D converters, RF transceivers, oscillators etc.

I guess this especially depends on the quality of the cell simulation models library. That could be the especially tough part about 14nm or Finfet designs in general. We don't know how good Intel will be doing on this but we definitely know that TSMC and the likes will soon face the same difficulties when porting designs from their existing 28/20nm to 16/14nm Finfets. Expect some delays here, especially for complex SoCs. 16nm Finfet TSMC SoC designs next year? Highly doubt it! Not even talking about Samsung 14nm Finfet SoCs.
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